1. Field of the Invention
The invention relates to the manufacture of very highly dense integrated circuits and more particularly to the method of formation of tapered contact openings to device elements of the integrated circuits. These device elements include device regions within the semiconductor substrate and metallurgy layers within a multilayer insulator and metallurgy structure.
2. Description of the Prior Art
Insulating multilayers are normally formed over the highly dense integrated circuits which are formed in and on a semiconductor substrate. These layers are thick in comparison to the feature size of one micrometer or less of the very dense integrated circuits which are now being manufactured. This thickness cannot be scaled down proportionately in the same way the feature size is scaled down. The layers are composed of silicon oxide, silicon nitride, glasses and the like insulators.
There are also multilayer insulator and metallurgy layers above the above mentioned insulating multilayers which connect the device structures within the semiconductor substrate into circuit structures. These layers are also thick in comparison to the feature size of one micrometer or less of the very dense integrated circuits which are now being manufactured. This thickness cannot be scaled down proportionately in the same way the feature size is scaled down. The layers are typically composed of silicon oxide, a silicate or siloxane spin-on-glass and silicon oxide composite layer.
It is necessary to make tapered contact openings through these above mentioned relatively thick insulating multilayers to the device elements formed in and on the semiconductor substrate and metallurgy layers within a multilayer of insulating and metallurgy layers. These openings are formed in the prior art by isotropic etching, anisotropic etching or a combination of these two etching techniques and heating steps to cause smoothing by flow of the insulator layer. A great amount of work and effort has been expended to find the best technique to form ideal tapered openings to the device elements. The need for tapered openings is so that the subsequent step of depositing a metal layer, for example aluminium will properly fill the opening and make an ohmic contact to the various device elements of the integrated circuit. Examples of patents that have tried to solve this problem are R. K. Berglund et al U.S. Pat. No. 4,902,377; M. H. Nemiroff U.S. Pat. No. 4,832,788; K. Shimokawa et al U.S. Pat. No. 4,908,333; Huebner U.S. Pat. No. 4,980,310; and B. Auda U.S. Pat. No. 4,814,041.
A copending patent application Ser. No. 07/713,508 filed Jun. 12, 1991 of C. S. Yoo, S. H. Kuo and T. H. Lin entitled "Contact Sidewall Tapering With Argon Sputtering" is directed to overcome the above mentioned heat to flow problem by using argon sputter etching rather than heat to flow the glass.
It has been recognized in the prior art that the high temperature heating that is generally used to flow the insulating layer, typically glass to smooth the sharp edges of contact opening can do damage to the integrated circuit device elements. For example, M. T. Bohr U.S. Pat. No. 4,372,034 describes a process wherein he uses a very deep isotropic etch through the glass insulating layer and then an anisotropic etch to pass through the thin silicon dioxide layer. He says that the high temperature heating step is not now required. However, this process can only be used in the past or where very simple and large size semiconductor devices are being made, because of the very large space taken up by the isotropic etch at each opening.
The high density integrated circuit devices wherein the feature sizes are less than about one micrometer or less have created very difficult problems involving the conservation of horizontal space. Also, there is the problem of the high temperature flow of the glass insulating layer for smoothing. The high temperature flow causes device problems, such as where a refractory silicide, for example titanium silicide is used in the conventional SALICIDE process. The major device problem caused in this instant is the high temperature increase in contact resistance due to silicide degradation. The longer thermal budget may degrade the submicron device performance.
The use of cured silicate or siloxane spin-on-glass layer is also generally known in the prior art and used in multilayer insulating layer and metallurgy composites to electrically connect the integrated circuit device. This may be better understood with reference to the Daniel L. Yen U.S. Pat. No. 5,003,062 entitled "Semiconductor Planarization Process for Submicron Devices".